Workshop and Tutorial Schedule
05/13/2026, Wednesday
| Time | Name | Organizer |
|---|---|---|
| 9 AM - 12 PM | CASI: Workshop on Custom Architectures for Scientific Instruments | Kazutomo Yoshii (Argonne), Tao Wei, Jon Calhoun (Clemson University), Peipei Zhou (Brown University) |
| 1:30 PM - 4:30 PM | Realizing Your Networking Research at 400Gbps Using Mango BoostX SmartNIC Powered by AMD Versal Premium FPGA | James C. Hoe (MangoBoost), Andrew Schmidt (AMD) |
05/16/2026, Saturday
| Time | Name | Organizer |
|---|---|---|
| 9 AM - 12 PM | Second Annual Workshop on Mixed Analog-Digital Configurable Adaptable Processing (MADCAP) | Jason D. Bakos, Ramtin Zand (Univ. of South Carolina), David Andrews (Univ. of Arkansas) |
| 1:30 PM - 4:30 PM | Next-Generation Adaptable Computing for Omics | Madhura Purnaprajna (AMD and PES University), Onur Mutlu, Konstantina Koliogeorgi (ETH Zurich), Marco Santambrogio (Politecnico di Milano) |
Abstracts
CASI: Workshop on Custom Architectures for Scientific Instruments, Chairs: Kazutomo Yoshii (Argonne), Tao Wei, Jon Calhoun (Clemson University), Peipei Zhou (Brown University)
Modern scientific instruments are producing data at unprecedented rates. For example,
next-generation X-ray detectors can approach one million frames per second, creating real-time processing demands that general-purpose systems struggle to meet due to I/O and latency limitations. Custom hardware architectures are therefore becoming essential for processing streaming data close to the sensor. At the same time, fully specialized hardware often lacks programmability, creating a need for programmable, ultra-low-latency architectures located on-chip or near the sensor.
This workshop will attract computer architects, FPGA/ASIC designers, and researchers
developing scientific instruments and experimental facilities. It will benefit participants interested in domain-specific acceleration, real-time data processing, and rapid hardware prototyping, and aims to foster collaboration across these communities.
Realizing Your Networking Research at 400Gbps Using Mango BoostX SmartNIC Powered by AMD Versal Premium FPGA. Chairs: James C. Hoe (MangoBoost), Andrew Schmidt (AMD)
Data movement has emerged as the central bottleneck for the most demanding large-scale AI and HPC systems, driving deployed link speeds to 800Gbps and motivating increased processing offloads into the NIC and switch. The time is ripe for academic research to innovate out-of-the-box solutions ahead of industry in a wide range of SmartNIC application opportunities, including protocol offloading, traffic shaping, network security, network virtualization, in-network processing, and high-frequency trading.
Though powerful, currently available commercial DPUs and SmartNICs often limit users to P4 for introducing custom line-rate, on-path processing. For greater generality, Ultrascale+-based AMD Alveo cards and Virtex-7-based NetFPGA SUME have been popular FPGA-based SmartNIC platforms for investigating novel custom on-path processing, but their performance and capacity have fallen behind present-day networking challenges. MangoBoost is offering its BoostX SmartNIC hardware as an up-to-
date platform for network research innovation.
The Mango BoostX SmartNIC comes with the Mango Shell development environment, ensuring networking researchers do not have to start their work from scratch. Mango Shell provides a strategically placed user-logic region enclosed by simplifying streaming interfaces. This dramatically lowers the barrier-to-entry for researchers new to FPGA-based SmartNICs or transitioning from previous FPGA platforms.
The goal of this tutorial is to explain how to use the features and abstractions provided by Mango shell to rapidly deploy custom on-path network processing on a Mango BoostX SmartNIC.
Second Annual Workshop on Mixed Analog-Digital Configurable Adaptable Processing (MADCAP). Chairs: Jason D. Bakos, Ramtin Zand (Univ. of South Carolina), David Andrews (Univ. of Arkansas)
Mixed analog-digital Processing-in-Memory (PIM) or Computing-in-Memory (CIM) technologies offer the potential to push GEMM and GEMV efficiencies to 1000 TOPs/Watt, but their primary barrier to widespread adoption is the efficiency loss caused by their integration with conventional processors and other coprocessors.
One approach is to tightly integrate PIM arrays into an FPGA or FPGA-like System-on-Chip, where the PIM array(s) comprise one facet of a heterogeneous system. To achieve this, the MADCAP workshop will bring together the FCCM and VLSI communities to collaborate and share ideas.
Next-Generation Adaptable Computing for Omics. Chairs: Madhura Purnaprajna (AMD and PES University), Onur Mutlu, Konstantina Koliogeorgi (ETH Zurich), Marco Santambrogio (Politecnico di Milano)
Omics disciplines—genomics, proteomics, metabolomics, and beyond—are generating data at unprecedented scales. Yet the computational demands of analyzing this data in real time remain a critical bottleneck, directly impacting our ability to deliver early diagnoses and life-saving care. As omics increasingly drives precision medicine and disease surveillance, overcoming these challenges is essential for timely, actionable insights in clinical settings.
While GPUs dominate many data-intensive workflows, they often fall short for the irregular, memory-bound, and fine-grained operations common in omics pipelines. Adaptable computing platforms—such as FPGAs, CGRAs, and dataflow architectures—offer a compelling alternative. Their reconfigurability enables tailored acceleration for diverse workloads, unlocking higher performance-per-watt and lower latency, both vital for scalable, cost-effective healthcare solutions. Despite this promise, adoption of adaptable architectures in omics remains limited. This workshop aims to galvanize the research community to bridge the gap between potential and practice. By uniting experts in architecture, systems, and computational biology, we seek to identify high-impact omics workloads where custom acceleration can enable earlier diagnoses and faster clinical decisions.
Key topics include evaluating current hardware/software readiness, identifying critical bottlenecks, and outlining the tools and infrastructure needed to support rapid development. We call on researchers, engineers, clinicians, and industry leaders to join this effort. By aligning architecture innovation with urgent healthcare needs, we can accelerate the translation of omics data into timely, life-saving interventions—and build a community committed to transforming the future of medicine.