FCCM 2024 Posters

Session A

Title	Authors
A Prototype-Based Framework to Design Scalable Heterogeneous SoCs with Fine-Grained DFS	Gabriele Montanaro, Andrea Galimberti, Davide Zoni (Politecnico di Milano)
Good Enough Is Perfect:Lowering the Barrier to VTR Interoperability with Error Resilient Cluster Reconstruction	Kate Thurmer, Mohamed A. Elgammal, Vaughn Betz (University of Toronto)
A Near-Sensor Image Processing Accelerator for Low-end FPGA Design	Peter Mbua, Zhaoqi Wang, Maximillian Panoff, Christophe Bobda (University of Florida)
Soft GPGPU versus IP cores: Quantifying and Reducing the Performance Gap	Martin Langhammer (Intel Corporation); George A. Constantinides (Imperial College London, UK)
if-ZKP: Intel FPGA-Based Acceleration of Zero Knowledge Proofs	Benjamin Reynolds, Shahzad Ahmad Butt, Pohrong Rita Chu, Veeraraghavan Ramamurthy, Xiao Xiao, Setareh Sharifian, Sergey Gribok, Bogdan Pasca (Intel Corporation)
Improving The Routing Performance of VTR 8 Under Resource Constraints	Junjie Hou (Huawei & Shanghai Jiao Tong University); Yue Zha, Jianjiang Zeng (Huawei); Jianguo Yao (Shanghai Jiao Tong University)
Kratos: An FPGA Benchmark for Unrolled Deep Neural Networks with Fine-Grained Sparsity and Mixed Precision	Xilai Dai, Yuzong Chen, Mohamed Abdelfattah (Cornell University)
SDAcc: A Stable Diffusion Accelerator on FPGA via Software-Hardware Co-Design	Hao Zhou, Yang Liu, Hongji Wang (Fudan University); Enhao Tang, Shun Li (Fuzhou Universiity); Yifan Zhang (Fudan University); Kun Wang (Fudan university)
Learned Index Acceleration with FPGAs: A SMART Approach	geetesh more (University of New brunswick); Suprio Ray (University of New Brunswick, Fredericton); Kenneth B. Kent (University of New Brunswick)
SpGCN: A FPGA based graph convolutional network accelerator for sparse graphs	Xiangzhi Xu, Qi Liu, Wenjin Huang, WenLu Peng, Yihua Huang (Sun Yat-sen University)
FlexFlow: A Programming Abstraction for Flexible Dataflow Support on Reconfigurable Accelerators	Shaojie Xiang, Niansong Zhang, Hongzheng Chen (Cornell University); Haiyu Wang (Peking University); Zhiru Zhang (Cornell University)
HBMorphic: Fully Homomorphic Encryption Acceleration via HBM-Enabled Recursive Karatsuba Multiplier on FPGA	Hassan Nassar (KIT); Lars Bauer, Jörg Henkel (Karlsruhe Institute of Technology)
Resource and Phase Awareness for Dynamically Scheduled High-Level Synthesis	Mathias Bouilloud (Imperial College London); Lana Josipovic (ETH Zurich); Wayne Luk (Imperial College London)
Energy-Aware Synchronization of Hardware Tasks in Multi-Tenant Systems	Cornelia Wulf, Gökhan Akgün (TU Dresden); Mehdi Safarpour (University of Oulu); Anastacia Grishchenko, Diana Göhringer (TU Dresden)

Session B

Title	Authors
OS4C: An Open-Source SR-IOV System for SmartNIC-based Cloud Platforms	Scott Smith, Yuan Ma, Marissa Lanz Kate, Bill Dai (University of Illinois Urbana-Champaign); Martin Ohmacht, Bharat Sukhwani, Hubertus Franke (IBM Research); Volodymyr Kindratenko (University of Illinois at Urbana-Champaign); Deming Chen (University of Illinois, Urbana-Champaign)
Variable Bit-width Random Number Generation for Implementing Direct Simulation Monte Carlo on Field-Programmable Gate Arrays	Saleen Bhattarai, Andrew Lambert, David Petty (The University of New South Wales Canberra); Sean O’Byrne (The Australian National University)
High-Performance Reconfigurable Accelerator for Knowledge Graph Reasoning	Hanning Chen, Ali Zakeri, Yang Ni (University of California, Irvine); Fei Wen (Texas A&M University); Behnam Khaleghi (University of California San Diego); Hugo Latapie (Cisco Systems); Mohsen Imani (University of California Irvine)
BitSys: Bitwise Systolic Array Architecture for Multi-precision Quantized Hardware Accelerators	Yuhao Liu, Salim Ullah, Akash Kumar (Chair of Processor Design, TU Dresden)
RingTK: A Ring, Parallel and High Performance Top-K Sorter on FPGA	Huawen Liang, Qizhe Wu, Wei Yuan, Teng Tian, Xi Jin (University of Science and Technology of China)
Stay Flexible: FPGA Acceleration of Graph Neural Networks on a High-Performance NPU Overlay	Taikun Zhang, Andrew Boutros (University of Toronto); Sergey Gribok, Kwadwo Boateng (Intel Corp.); Vaughn Betz (University of Toronto)
AXI SmartDisconnect: Guiding Memory Performance in Multi-Tenant FPGAs	Kristiyan Manev (EnduroSat)
The BRAM is the Limit: Shattering Myths, Shaping Standards, and Building Scalable PIM Accelerators	MD Arafat Kabir, Tendayi Kamucheka, Nathaniel Fredricks (University of Arkansas); Joel Mandebi (Advanced Micro Devices, Inc. (AMD)); Jason Bakos (University of South Carolina); Miaoqing Huang, David Andrews (University of Arkansas)
Best of Both Worlds: Integrating Scalable Analytical Placement into the Flexible VTR Framework	Rachel Selina Rajarathnam (University of Texas at Austin, Austin, TX, USA); Kate Thurmer, Vaughn Betz (University of Toronto, Toronto, ON, Canada); Mahesh A. Iyer (Intel Corporation, San Jose, CA, USA); David Z. Pan (University of Texas at Austin, Austin, TX, USA)
Etna: MLIR-Based System-Level Design and Optimization for Transparent Application Execution on CPU-FPGA Nodes	Stephanie Soldavini (Politecnico di Milano); Felix Suchert (TU Dresden); Serena Curzel, Michele Fiorito (Politecnico di Milano); Karl Friedrich Alexander Friebel (TU Dresden); Fabrizio Ferrandi (Politecnico di Milano); Radim Cmar (Sygic); Jeronimo Castrillon (TU Dresden); Christian Pilato (Politecnico di Milano)
Efficient profiling of HLS code	Kimberley Stonehouse, Jose Lopes, Benoit Pradelle (AMD)
Fitop-Trans: Maximizing Transformer Pipeline Efficiency through Fixed-Length Token Pruning on FPGA	Kejia Shi, Manting Zhang, Keqing Zhao, Xiaoxing Wu, Jun Yu, Kun Wang (Fudan University)