Keynote 2024

Keynote I: Can Deep Learning Broaden the Participation of FPGA Designs?

Jason Cong

UCLA Computer Science Department

Director, Center for Domain-Specific Computing (CDSC)


Given that there are at least 30X more software designers than hardware designers based on the data from US Bureau of Labor Statistics, it is important to get many more software programmers to participate in the creation and use of field-programmable custom computing machines (FCCMs) or FPGA accelerators in short. The FPGA design barrier has been lowered considerably with the introduction of high-level synthesis (HLS), but it remains a challenge to explore the large design space offered by HLS and quickly converge to the best solution. In the past decade, deep learning has shown promising results on many applications, such as image recognition, natural language processing, and protein folding.

In this talk, I present our latest research on using deep learning to automate FPGA designs. By coupling HLS with a set of deep learning techniques, such as graph-based neural networks, transfer learning, and large language models, we achieved promising results on both HLS quality prediction and design space exploration for general applications. When coupled microarchitecture guided optimization for regular structures, such as systolic arrays and stencil computation, we show that it is possible to automate IC designs so that many software programmers can design their own FPGA accelerators for a wide range of applications, potentially greatly broaden the FCCM community.


JASON CONG is the Volgenau Chair for Engineering Excellence Professor at the UCLA Computer Science Department (and a former department chair), with joint appointment from the Electrical and Computer Engineering Department. He is the director of Center for Domain-Specific Computing (CDSC) and the director of VLSI Architecture, Synthesis, and Technology (VAST) Laboratory.  Dr. Cong’s research interests include novel architectures and compilation for customizable computing, synthesis of VLSI circuits and systems, and quantum computing.  He has over 500 publications in these areas, including 18 best paper awards, and 4 papers in the FPGA and Reconfigurable Computing Hall of Fame.  He and his former students co-founded AutoESL, which developed the most widely used high-level synthesis tool for FPGAs (renamed to Vivado HLS and Vitis HLS after Xilinx’s acquisition).   He is member of the National Academy of Engineering, and a Fellow of ACM, IEEE, and the National Academy of Inventors.   He is recipient of the SIA University Research Award, the EDAA Achievement Award, and the IEEE Robert N. Noyce Medal for “fundamental contributions to electronic design automation and FPGA design methods”.

Keynote II: Pets vs Cattle: Heterogeneous Systems in the 21st Century.

Miriam Leeser

Northeastern University

Director, Reconfigurable and GPU Computing Laboratory (RCL)


Decades ago computers were pets. They sat on our desktops, had names and we cared for them as individuals. More recently, in addition to pets, computers have become cattle. They are out in the field, are identified by numbers, and if one dies it is replaced without associated mourning. The same transition is happening to hardware accelerators, including Graphics Processing Units (GPUs) and Field Programmable Gate Arrays (FPGAs), which can now be considered cattle in cloud computers. A new model for cloud computing is disaggregation, which allows users to flexibly acquire and allocate the computing resources they need. The serverless programming model provides an abstraction for decomposing applications to map onto disaggregated hardware. Such disaggregated hardware is frequently connected directly to the network without the need or delay associated with host intervention.

In this talk, I will focus on network-attached FPGAs available in the Open Cloud Testbed (OCT) I will discuss the hardware model and programming paradigm of accelerators as cattle and applications that benefit from hardware directly to the network. I will also discuss security issues that arise from this model. Network-connected hardware can serve both as an attacker and as a defender from security breaches. FPGAs usually do not run an operating system, so there are no checks on the data sent out on the network. Thus, they can easily launch attacks such as Denial of Service (DoS) by flooding the network with packets. These FPGAs can also monitor traffic on the network directly, and identify such attacks. Nowadays, FPGAs are both pets and cattle, as well as having the potential to be either the attacker or the defender in disaggregated cloud computing. Whatever the question, FPGAs are the answer.


Miriam Leeser has been designing with FPGAs since they first emerged as pets.  She is a Professor of Computer Engineering at Northeastern University and head of the Reconfigurable Computing Laboratory.  She has conducted research in floating point implementations, unsupervised learning, medical imaging, and privacy preserving data processing.  Throughout her career, she has been funded by both government agencies and companies, including AMD, DARPA, NSF, Google, and MathWorks. She is the recipient of a Fulbright Scholar Award and a Charter Member of the IEEE Computer Society Distinguished Contributor Recognition Program.   Her current research focus is on FPGAs for wireless communications as well as FPGAs in the data center.