Poster Session 1
| Title | Authors |
|---|---|
| HESP-Stream: A Sensor-Direct, Instruction-Driven FPGA System for Real-Time Sparse Event Processing | Jihui Qi, Yongjiang Xue, Qingzeng Song (Tiangong University) |
| AutoINV: Automated Invariant Generation Framework for Formal Verification on High-Level Synthesis Designs | Xiaofeng Zhou, Linfeng Du, Guangyu Hu (The Hong Kong University of Science and Technology); Sharad Sinha (Indian Institute of Technology Goa); Hongce Zhang, Jiang Xu (The Hong Kong University of Science and Technology (Guangzhou)); Wei Zhang (The Hong Kong University of Science and Technology) |
| LiveGraph: High-Performance On-FPGA Dynamic Graph Updating Framework | Yufeng Luo, Peikun Hong, Jing Wang (Shanghai Jiao Tong University); Feiyang Wu (Peking University); Chao Li, Minyi Guo (Shanghai Jiao Tong University) |
| Accelerating Topology Optimization on AMD Versal AIE-ML Engines | Kaustubh Manohar Mhatre, Vedant Tewari, Aditya Ray (Arizona State University); Farhan Khan (Technical University of Munich); Ridwan Olabiyi, Ashif Iquebal, Aman Arora (Arizona State University) |
| SIFT: LLM-Assisted Assertion Generation for On-Chip Protocol Implementations | Melisande Zonta-Roudes, Nora Hinderling, Supraja Sridhara (ETH Zurich); Srinidhi Nagendra (Max Planck Institute for Software Systems); Shweta Shinde (ETH Zurich) |
| Streaming Sparse Matrix Multiplication on FPGAs via Sparsity-Aware Data Reordering | Shuxuan Li, Wim Vanderbauwhede, Nikela Papadopoulou (University of Glasgow) |
| STEEL: Sparsity-Aware Fused Attention for Energy-Efficient Long-Sequence Inference on AMD’s XDNA™ NPU | Victor J. B. Jung (ETH Zurich & AMD); Gagandeep Singh, Joseph Melber, Kristof Denolf (AMD); Francesco Conti (University of Bologna); Luca Benini (ETH Zurich & University of Bologna) |
Poster Session 2
| Title | Authors |
|---|---|
| MLIR-DPR: A Compiler Framework for Automating Dynamic Partial Reconfiguration | Gabriel Rodriguez-Canal, Nick Brown (EPCC, University of Edinburgh); Maurice Jamieson (EPCC University of Edinburgh); Nicolas Bohm Agostini, Ankur Limaye, Vito Giovanni Castellana, Josepth Manzano, Antonino Tumeo (Pacific Northwest National Laboratory) |
| Chariot: Compiler-Aware Heterogeneous Graph Representation Learning for Automated HLS Optimization | Yanlong Huang, Jierui Liu, Yuhan She (The City University of Hong Kong); Rongliang Fu, Tsung-Yi Ho (The Chinese University of Hong Kong); Hong Yan, Ray C.C. Cheung (The City University of Hong Kong) |
| DTCore: A Compiler-Directed Control-Minimal FPGA Compute Engine | Wei-Cheng Zeng, Kuan-Ting Lai (National Taipei University of Technology) |
| Utilising Pipelined Buses to Provide Resource Efficient Dynamic Thread Scheduling in Barrel Scheduled Processors | Thomas Bain, David Thomas, Graeme Bragg (University of Southampton) |
| Design Space Exploration for Layer Pipelined DNN Accelerators Based on FPGAs | Yiwei Wang, Chang Wu (Fudan University) |
| A Hybrid Ising FPGA-COBI Architecture with Hardware Based Problem Decomposition | Ruihong Yin, Yue Zheng, Chaohui Li, Ahmet Efe, Abhimanyu Kumar, Ziqing Zeng, Ulya R. Karpuzcu, Sachin S. Sapatnekar, Chris H. Kim (University of Minnesota) |
| Precision-aware Communication in CGRAs | Shwet Chitnis, Fergus Xu, Ayush Kulkarni, Jiayi Wang, Jingqun Zhang (University of Washington); Arjun Raje (Carnegie Mellon University); Ang Li (University of Washington) |
| Towards Small Language Models on FPGAs with A-PACE: Attention Precision & Accumulation Co-design Explorer | Filip Wojcicki, Omar Sharif, Ebby Samson, Paul H. J. Kelly, George A. Constantinides, Christos-Savvas Bouganis (Imperial College London); Wayne Luk (Imperial College) |
| SCOPE: SCalable and Observable PEripheral-Borrowing Framework for FPGA-Based Prototyping | Jiarun Yan, Ao Liu, Si Zhang, Congwu Zhang, Yazhou Wang, Shiqi Liu, Ke Zhang (Institute of Computing Technology, Chinese Academy of Sciences) |
| LENS-HLS: LLM-Enhanced Learning-based Design Space Exploration for High-Level Synthesis | Yujie Yan, Guanhua Chen, Keren Zhu (Fudan University) |
| ForgeBench: A Machine Learning Benchmark Suite and Auto-Generation Framework for Next-Generation HLS Tools | Andy Wanna, Hanqiu Chen, Cong Hao (Georgia Institute of Technology) |
Poster Session 3
| Title | Authors |
|---|---|
| An Efficient Dataflow Framework for DiT-Based Image Generation | Yazhe Zhang, Shouyu Du, Zhenyu Xu, Miaoxiang Yu, Dingjiang Yan, Zhiheng Ni (Clemson University); Qing Yang (The University of Rhode Island); Tao Wei (Clemson University) |
| DORA: Dataflow-Instruction Orchestration Architecture for DNN Acceleration | Xingzhen Chen, Zhuoping Yang, Jinming Zhuang, Shixin Ji, Sarah Schultz (Brown University); Zheng Dong (Wayne State University); Weisong Shi (University of Delaware); Peipei Zhou (Brown University) |
| HAMG: A Hierarchical Automated MemTile-based GEMM Accelerator for Versal AIE-ML | Kai Shao (Southeast University); Erwei Wang (AMD); He Li (Southeast University) |
| CrossFuse: A Fused Mixed-Precision kernel Library for Efficient Quantized LLM Inference on XDNA NPU | Wesley Pang, Gregory Jun, Feiyang Liu, Deming Chen (University of Illinois Urbana-Champaign) |
| Lightweight Lossless Compression Scheme for Video Applications on Versal ACAP Devices | Sharan Kumar, Sandesh Goyal, Atreyee Saha, Srini Srinivasan, Aashish Tripathi (AMD) |
| FAST-Prefill: FPGA Accelerated Sparse Attention for Long Context LLM Prefill | Rakshith Jayanth, Viktor Prasanna (University of Southern California) |
| Lightweight Queueing Abstraction for Rapid Simulation and Automated Tuning of Input-Dependent Streaming Pipelines on FPGAs | Shashank Obla (Carnegie Mellon University); Bin Li (Intel); James Hoe (Carnegie Mellon University) |
| EDSSC: An Efficient FPGA-based Accelerator for Dynamic Sparse Spectral Clustering | Zhengyan Liu (Tianjin University / Imperial College London); Ce Guo, Zehuan Zhang (Imperial College London); Qiang Liu (Tianjin University); Wayne Luk (Imperial College) |
| Combining HLS and Computation Coding for Balanced Matrix-Vector Engines on FPGA | Sayanti Pal, Alexander Lehnert, Marc Reichenbach (University of Rostock) |
| Sparse Compressed Quantized Dataflow Architecture (QUDA) for Neuromorphic Computing | Shadi Matinizadeh, Anup Das (Drexel University) |
| Efficient Split-Posit DSP Slice Architecture for Embedded FPGA Fabrics | Arun M, Madhav Rao (IIIT Bangalore) |