FCCM 26 Program
*All times shown in the Atlanta local time, EDT (UTC-4)
Wednesday – May 13 (Workshops, Tutorials, fun evening events)
Location: CODA Building; More details see: Workshops and Tutorials
Registration: Room 113
| 8:00 AM – 9:00 AM | Breakfast (CODA first floor) |
| 9:00 AM – 12:00 PM | – CASI: Workshop on Custom Architectures for Scientific Instruments (Room 114) – Tutorial: Intelligent Tools and Frameworks for FPGA Design (Room 230) |
| 12:00 PM – 1:30 PM | Lunch |
| 1:30 PM – 4:30 PM | – Realizing Your Networking Research at 400Gbps Using Mango BoostX SmartNIC Powered by AMD Versal Premium FPGA (Room 114) – The 5th Workshop on Security for Custom Computing Machines (SCCM) (Room 230) |
| 4:30 PM – 6:00 PM | Break |
| 6:00 PM – 8:00 PM | Reception + Social Event (Host: Peipei Zhou and Ron Sass) Location: CODA Atrium 9th floor (escort needed) Mini-debates FCCM 2026 Top 10 Predictions |
Thursday – May 14 (Main conference, keynote, demo night)
Location: Georgia Tech Global Learning Center, Room 236
★ indicates best paper candidate
Code Available
Code Reviewed 
Code Reproducible 
| 7:30 AM – 8:30 AM | Breakfast |
| 8:30 AM – 8:45 AM | Welcoming Remarks |
| 8:45 AM – 9:30 AM | Keynote 1 – Trust at Scale with Hardware‑Assisted Verification: Rethinking Custom Computing Machines Dr. Sridhar Seshadri (Synopsys) |
| 9:30 AM – 10:10 AM | Session 1 – CAD 1 (Chair: Chris Lavin, AMD) |
| The Optimal, The Fast, and The Hybrid: Automatic Placement and Routing for AIE Arrays ★ Hang Yan, James Yen, Rongbo Zhang (University of Toronto); Andrew Boutros (University of Waterloo); Vaughn Betz (University of Toronto) | |
| Déjà Vu Packing: Optimizing FPGA Logic Clustering Runtime via Pattern Memoization Milo Liebster (University of Waterloo); Amin Mohaghegh (QuickLogic Corporation); Andrew Boutros (University of Waterloo) | |
| 10:10 AM – 10:50 AM | Poster Session 1 & PhD Forum & Coffee Break |
| 10:50 AM – 11:55 AM | Session 2: Neural Network Architectures and Acceleration (Chair: Peipei Zhou, Brown University) |
| HGQ-LUT: Fast LUT-Aware Training and Efficient Architectures for DNN Inference ★ Chang Sun (California Institute of Technology); Zhiqiang Que, Bakhtiar Zadeh (Imperial College London); Qibin Liu (SLAC National Accelerator Laboratory); Kevin Halm Alvarez, Wayne Luk (Imperial College London); Maria Spiropulu (California Institute of Technology) | |
| FHPSAC: FPGA-based High-Parallelism SAC Accelerator ★ Jiabin Xu, Wang Fan, Xuegong Zhou, Wei Cao, Jialin Chen, Fengzhe Zhang, Fan Zhang (Institute of Big Data, Fudan University); Xinsheng Yu (The 32nd Research Institute of China Electronics Technology Group Corporation) | |
| GraphLeap: Decoupling Graph Construction and Convolution for Vision GNN Acceleration on FPGA Anvitha Ramachandran, Dhruv Parikh, Viktor Prasanna (University of Southern California) | |
| Δ2-PSUM: A Low-Latency Soft-Error-Resilient Binary Neural Network Inference Processor Sae-Byeok Jeong, Tae-Hwan Kim (Korea Aerospace University) | |
| 11:55 AM – 1:25 PM | Lunch |
| 1:25 PM – 2:45 PM | Session 3: Networking and Systems (Chair: Davide Conficconi, Politecnico di Milano) |
| NetCilk: Extending Task-Level Parallelism Seamlessly Across FPGAs ★ Mohamed Mahfouz Shahawy, Canberk Sonmez, Paolo Ienne (EPFL) | |
| EZCache: Easy Action-Enabled FPGA Caches for Non-Stalling Datapaths in SmartNICs and Beyond Ahmed Abdelsalam, Vishal Gondaliya (Microsoft); Ezz Hamed (Meta), Pragati Medleri Hire Math, Marc Gepigon, Joshua Landgraf, Nadeen Gebara, Bob Groza, Dongwook Lee, Anshuman Verma, Andrew Putnam (Microsoft) | |
| SPAC: Automating FPGA-based Network Switches with Protocol Adaptive Customization Guoyu Li, Yang Cao, Lucas H L Ng, Alexander Charlton, Qianzhou Wang, Will Punter (Imperial College London); Philippos Papaphilippou (University of Southampton); Ce Guo, Hongxiang Fan, Wayne Luk (Imperial College London); Saman Amarasinghe, Ajay Brahmakshatriya (Massachusetts Institute of Technology) | |
| A Robotics Middleware for FPGAs Supporting Dynamic Function Exchange and Streaming Data Distribution Alexander Philipp Nowosad, Christian Lienen, Marco Platzner (Paderborn University) | |
| 2:45 PM – 3:25 PM | Poster Session 2 & Coffee Break |
| 3:25 PM – 4:30 PM | Session 4: AI Inference (Chair: Jeff Goeders, BYU) |
| ViM-Q: Scalable Algorithm-Hardware Co-Design for Vision Mamba Model Inference on FPGA Shengzhe Lyu, Yuhan She, Patrick S. Y. Hung, Ray C. C. Cheung, Weitao Xu (City University of Hong Kong) | |
| ReCoVLM: A Reconfigurable FPGA–GPU Co-Design for Edge Vision-Language Inference Jingyu Wang, Yongjiang Xue, Kailai Zhuang, Mingze Sun, Qingzeng Song (Tiangong University) | |
| LUT-LLM: Efficient Language Model Inference with Memory-based Computations on FPGAs Zifan He (University of California, Los Angeles); Shengyu Ye (Microsoft Research); Rui Ma (Microsoft Research Asia); Yang Wang (Microsoft Research); Jason Cong (UCLA) | |
| VSALUT: A Lightweight Low-Dimensional VSA Classifier for Efficient Inference on FPGA Nuntipat Narkthong, Xiaolin Xu (Northeastern University) | |
| 4:30 PM – 5:15 PM | Reconfigurable Computing Challenge RCC finalist presentations |
| 6:30 PM – 8:30 PM | Demo Night with Reception Hardware/Software solutions, student demo, sponsor demo, RCC finalist design demo |
Friday – May 15 (Main conference, panel, award ceremony)
| 7:30 AM – 8:30 AM | Breakfast (Sponsored by Optiver) |
| 8:00 AM – 8:30 AM | Optiver Technical Talk: Kevin Sprague (FPGA Engineering Lead) Full-Stack FPGA Engineering: Optimizing the Whole System “Sometimes the best FPGA algorithm is discovered through software; sometimes the best software is made possible by new FPGA architecture. Full-stack FPGA engineering means understanding the entire system well enough to implement each solution in the right place.” |
| 8:30 AM – 9:30 AM | Session 5: CAD 2 (Chair: Andrew Boutros, University of Waterloo) |
| DiffRouter: A Differentiable Routing Framework for UltraScale FPGAs Xiaohan Gao, Zhili Xiong (The University of Texas at Austin); Yusu Wang (University of California San Diego); David Z. Pan (The University of Texas at Austin) | |
| PathSteiner: Improving PathFinder with Quasi-Optimal Steiner-Tree Initialization Shashwat Shrivastava, Luka Kurešević, Alexandros Poupakis (EPFL); Chirag Ravishankar, Dinesh Gaitonde (AMD); Stefan Nikolić (University of Novi Sad); Mirjana Stojilović (EPFL) | |
| Enabling Net-Level Global Vision in FPGA Routing via Precomputed Steiner Potential Fields YaoZhang Liu (College of Integrated Circuits & Micro-Nano Electronics, Fudan University) | |
| 9:30 AM – 10:00 AM | Coffee Break |
| 10:00 AM – 11:30 AM | Panel AI+HW for Reconfigurable Computing: Shaping the Next Decade Moderator: Prof. Deming Chen (UIUC) |
| 11:30 AM – 12:15 PM | Session 6: Reconfigurable Architectures and Arithmetic (Chair: Suhaib Fahmy, King Abdullah University of Science and Technology) |
| Enabling Context-Switchable Monolithic 3D FPGA Design Using Bistable Ferroelectric Inverters Faaiq Waqar, Matthew Chen (Georgia Institute of Technology); Zifan He (University of California Los Angeles); Zishen Wan, Minji Shon, Wei-Hsing Huang (Georgia Institute of Technology); Jason Cong (University of California Los Angeles); Shimeng Yu (Georgia Institute of Technology) | |
| ReFHE-NTT: Resource-Driven NTT FPGA Architecture for Fully Homomorphic Encryption Valentino Guerrini, Sorrentino Giuseppe, Alessandro Barenghi, Davide Conficconi (Politecnico di Milano) | |
| TransDot: An Area-efficient Reconfigurable Floating-Point Unit for Trans-Precision Dot-Product Accumulation with Emerging AI Formats Jiayi Wang, Maohua Nie, Sin-Chen Lin, C.-J. Richard Shi, Ang Li (University of Washington) | |
| 12:15 PM – 1:45 PM | Lunch |
| 1:45 PM – 3:05 PM | Session 7: AI Engines (Chair: Antonino Tumeo, Pacific Northwest National Laboratory) |
| AIE4ML: An End-to-End Framework for Compiling Neural Networks for the Next Generation of AMD AI Engines Dimitrios Danopoulos, Enrico Lupi, Chang Sun (European Organization for Nuclear Research (CERN), Geneva, Switzerland); Sebastian Dittmeier (Physikalisches Institut, Heidelberg University, Germany); Michael Kagan (European Organization for Nuclear Research (CERN), Geneva, Switzerland); Vladimir Loncar (Institute of Physics Belgrade, Serbia); Maurizio Pierini (European Organization for Nuclear Research (CERN), Geneva, Switzerland) | |
| When Systolic Arrays Meet AI Engines: Architectural Constraints on AMD Versal ACAP Jason Kimko, Jason Cong (UCLA) | |
| Adaptive AIE–PL Systems for Efficient End-to-End Pyramidal 3D Image Registration Sorrentino Giuseppe, Paolo Salvatore Galfano, Claudio Di Salvo (Politecnico di Milano); Eleonora D’Arnese (University of Edinburgh); Davide Conficconi (Politecnico di Milano) | |
| LegoMap: Optimization for High-Throughput Transformer Computing on AI Engine-Based FPGAs Hailiang Hu, Haodong Chang, Donghao Fang, Zhenrui Wang (Texas A&M University); Wuxi Li (AMD, Inc.); Rongjian Liang (Nvidia); Bo Yuan (Rutgers University); Jiang Hu (Texas A&M University) | |
| 3:05 PM – 3:45 PM | Poster Session 3 & Coffee Break |
| 3:45 PM – 5:10 PM | Session 8: Applications (Chair: Madhura Purnaprajna, AMD) |
| Hardware stencil accelerator with periodic boundary conditions Damien Simon (INRIA); Olivier Sentieys (Univ. Rennes, Inria); Sylvain Lefebvre (INRIA) | |
| Trident: Efficient FPGA Acceleration of XMSS Tree in Post-Quantum Signature Scheme SLH-DSA Tianyou Bao (Villanova University); Joshua Ennis, Kirill Morozov (University of North Texas); Jiafeng Xie (Villanova University) | |
| ImageHD: Energy-Efficient On-Device Continual Learning of Visual Representations via Hyperdimensional Computing Jebacyril Arockiaraj, Dhruv Parikh, Viktor Prasanna (University of Southern California) | |
| FASTR: FPGA-based Acceleration of Hierarchical Foundation Models for SAR ATR Sachini Wickramasinghe, Cauligi Raghavendra, Viktor Prasanna (University of Southern California) | |
| AccelOrb: FPGA Acceleration of Orb v2 for Fast Molecular Dynamics Sunjae Kim, Gwanhong Park, Jeawoo Lim, Faaiz Asim, Jongeun Lee (Ulsan National Institute of Science and Technology) | |
| 5:10 PM – 5:25 PM | Best Paper Award & Closing Ceremony |
| 6:00 PM – 8:00 PM | Social Event Sponsored by Optiver Location: Georgia Tech Hotel Pre-functional Room |
Saturday – May 16 (Workshops)
Location: Georgia Tech Hotel; More details see: Workshops and Tutorials
| 8:00 AM – 9:00 AM | Breakfast (GT Hotel second floor) |
| 9:00 AM – 12:00 PM | Second Annual Workshop on Mixed Analog-Digital Configurable Adaptable Processing (MADCAP) (GT Hotel Conference Room 1) Next-Generation Adaptable Computing for Omics (GT Hotel Conference Room 2) |